1. Field of the Invention
The present invention is related to Integrated Circuits (ICs) and, more particularly, to ICs having air dielectric wiring for reduced capacitance.
2. Background Description
Integrated circuit (IC) performance is dependent upon individual circuit performance. Individual circuit performance is dependent on the load the circuit must drive. For field effect transistor (FET) circuits, the primary load is capacitive. The primary source of the circuit load capacitance is inter-circuit wiring capacitance. Thus, IC performance can improved by reducing wiring capacitance.
Typical IC chips with a large number of logic circuits include multiple layers of wires, called wiring layers, stacked one on top of another and separated by dielectric material. The ideal dielectric is air or, at least has the same dielectric constant as air. There are several approaches to providing an air dielectric in IC chips.
Freestanding Structures
One approach is to remove the dielectric around the wires, suspending the wiring in air. The suspended wires are uncovered with any dielectric and are supported, mechanically, only by interlevel metal studs used to form the circuit. Although scanning electron microscopic (SEM) images of such structures clearly show that small lengths of wire are self supporting, longer lengths of wire are not self-supporting. So, longer lengths of unsupported wire are susceptible to shorting.
For example, U.S. Pat. No. 4,899,439 entitled "Method of Fabricating A High Density Electrical Interconnect" to Potter et al. teaches building pillars from the substrate under the wires extending upward to upper wiring levels wherever support is required. However, because wiring channels must be allocated for these pillars, the pitch or density of wires is reduced by as much as half.
Another approach is to stiffen the wires, such as taught in U.S. Pat. No. 5,148,260 entitled "Semiconductor Device Having an Improved Air Bridge Lead Structure" to Inoue et al., wherein the metal lines are formed from a stiffer composite metal that is less likely to deform than typical wiring metals. This approach reduces, but does not eliminate shorting in an air dielectric IC structure. Further, Inoue et al., also requires including some support pillars, although not as many are required as in Potter et al.
Both Potter et al- and Inoue et al teach structures that are formed using conventional techniques, with the removable dielectric material removed through several repeating layers of metal studs and metal lines. Material may be backfilled around the freestanding wires to provide a dielectric other than air.
Gravity is the primary focus in abating shorting problems in prior art freestanding IC wiring structures. Thus, to counteract gravity, a strong support is provided from below the wires.
The above examples of the prior art incur a substantial wiring density penalty because the support pillars extend through several wiring levels, all the way up from an underlying substrate. These small diameter support pillars are formed level by level and so, must be lined up at each level with an underlying level.
To simplify this critical alignment requirement, a stiff intermediate planar layer may be formed on each support pillar level. Thus, the pillars would support the planar layer and the planar layer supports another pillar level. For this type structure, pillars need not line up from level to level. However, any dielectric must be removed after the planar layer is formed by complex venting and filling steps or the dielectric is trapped under the permanent planar layer.
A typical prior art approach, when using planar layers to construct freestanding structures, is to form an air dielectric on a layer by layer basis. For example, in U.S. Pat. No. 5,144,411 entitled "Method and Structure for Providing Improved Insulation in VLSI and ULSI Circuits", to Kaanta et al. (hereinafter Kaanta), a planar layer is formed above metal lines or on pedestals above the metal lines with a complex process requiring extra masks. Kaanta teaches etching access openings through the planar layer, removing the dielectric, plugging the openings, and then, continuing construction of subsequent layers.
U.S. Pat. No. 5,444,015 entitled "Larce (sic) Scale IC Personalization Method Employing Air Dielectric Structure for Extended Conductors" to Aitken et al. (Hereinafter Aitken), assigned to the assignee of the present invention, teaches an approach similar to Kaanta that reduces the extra masks by forming openings in a removable dielectric for studs and supports simultaneously.
The support dimensions in Aitken are much smaller than studs. After forming support openings, Aitken teaches depositing dielectric to dill the support locations and line stud openings. An anisotropic etch removes support dielectric at the bottom of the stud openings that are filled with metal in subsequent steps. Unfortunately, Aitken stud opening diameters must be significantly wider (twice the thickness of the dielectric tube) than the studs themselves, which must be significantly larger than the minimum process dimension.
Prior art structures are, typically, supported by pedestals. The circuit design tools must keep track of whether inter-level features are studs or pedestals. Further, circuit design is more complicated because the wiring and the support pedestals must be accounted for on each wiring level.
Materials and Processing
Materials used in prior art methods are exotic and, so, are expensive to develop and difficult to remove. Kaanta, for example, teaches using parylene as a removable dielectric. Parylene has a low decomposition temperature, which severely restricts the materials that can be used for the freestanding structures.
Furthermore, typical prior art methods use aqueous chemicals to etch the removable material. It is uncertain whether these aqueous chemicals can penetrate the convoluted paths to regions buried deep within the wiring that must be cleared of removable dielectric. In particular, when dielectric removal is deferred until the end, or, for structures with vented planar layers such as U.S. Pat. No. 5,324,683 to Fitch et al. entitled "Method of Forming a Semiconductor Structure having an Air Region" (which is even more complex than Kaanta), these aqueous chemicals penetrate vent holes with considerable difficulty.
Further, after reaction and drying, the reaction products may not be removed completely from the nearly enclosed air dielectric compartments. These small openings make it difficult for reactants to diffuse in, or for waste products to diffuse out, when the cavities are filled with a liquid.
Additional problems arise when aqueous HF is used to remove oxides from the exposed metal lines. The HF in the aqueous solution can attack the metal, especially when the lines are a composite metal. Electrochemical potentials further contribute to corrosion of one metal of the composite. Such an attack can result in open electrical circuits, higher line resistivity, and the metal lines separating from their supports.
Thus, there is a need for a way to remove dielectric from metal lines without attacking the metal, with adequate penetration of small openings and subsequent removal of reaction waste products from the structure. Further there is a need for a way to form air dielectric structures on integrated circuit chips without increasing the number of masks, requiring complex vent and fill procedures or difficult support alignment.